1. Field of the Invention
This invention generally relates to the field of a design for a fault toleration circuit. More particularly, the present invention relates to a memory modeling circuit with fault toleration.
2. Description of the Prior Art
Many devices require memory systems with high reliability, such as servers in enterprises or government offices; mainframes in financial institutions; equipment in hospitals; navigation systems for aircrafts or spaceships; even the devices used in severe environments. The memory systems with high reliability are required in order to ensure the accuracy of data and make whole system work regularly since the memory systems in those devices are used in storing important data.
In order to improve the reliability of memories, well-known methods are to add testing items to memories for picking those defected out before their leaving the factor; to disable or discard error bit and even to correct it by software detecting/debugging.
Although the reliability of memory can be effectively improved in real time by software detecting/debugging, the only one way is to replace a new one while the data stored in the memory occurs numerous errors. As to other methods, they cannot detect error in real time but only compensation.
This is, one bit error or a few data errors can be processed in real time by adopting software detecting/debugging method. However, the whole system will shut down and lose the important data stored in memory while numerous data errors occur in the memory. As to other methods, they only can improve the product reliability in the future by analyzing the historical errors but cannot deal with the error in real time.
Therefore, there is a need for providing a memory modeling circuit with fault toleration that can detect and correct error(s) in real time.